The present invention relates generally to computer processors, and more specifically, to collision-based alternate hashing in a processor.
In a computing system, the main computer memory may be relatively slow compared to the computer processor; therefore, one or more caches may be provided in the processor to reduce or avoid accesses to the main memory. A cache is a relatively small, high-speed buffer of memory placed between the processor and the main memory that holds most recently used sections of the main memory for use by the processor. The sections of memory that are stored in the cache are referred to as a cache lines. Any request made by the processor that is satisfied by the cache may be completed relatively quickly. However, when a request by the processor is not satisfied by the cache, a cache miss occurs, which may cause delays in the processor while the request is satisfied from the main memory.
Prefetching is a technique that is used to reduce delays to the processor caused by cache misses. Prefetching attempts to predict requests (for example, requests for instructions or operands) that will be made by the processor and stage lines of memory into the cache before the processor requests them. If prefetching is successful, cache lines are transferred from the main memory into the cache before the processor requests them, avoiding cache misses and reducing overall latency in the processor. Prefetching may be performed based on a history table that holds the recent history of instructions in the processor indexed by instruction address. Event streams, including cache misses, associated with particular instruction addresses that appear repeatedly during program execution may form patterns that trigger insertion of prefetch requests into the processor pipeline.